Electrostatic discharge (ESD) is a continuing problem in the design, manufacture, and utilization of integrated circuits (ICs). A major source of ESD exposure to ICs is from the human body (described by the “Human Body Model”, HBM). In this situation, a packaged IC acquires a charge when it is touched by a human who is electrostatically charged (e.g. from walking across a carpet). A charge of about 0.4 uC may be induced on a body capacitance of 100 pF, for example, leading to an electrostatic potential of 4 kV or more and discharge peak currents of several amperes to the IC for longer than 100 ns. A second source of ESD exposure is from charged metallic objects (described by the “Machine Model”, MM), which is characterized by a greater capacitance, lower internal resistance and transients that have significantly higher peak current levels than a HBM ESD source. A third source of ESD exposure is due to the discharge of stored charge on the integrated circuit itself (described by the “Charged Device Model”, CDM), to ground with rise times of less than 500 ps. The current flow during CDM is in the opposite direction of the HBM and MM ESD sources. For all three sources of ESD exposure, both positive and negative polarity discharges may occur.
Shallow trench isolation (STI) spaced diodes in which an N+ to pwell diode is isolated from a pwell contact by STI is one type of ESD protection diode commonly used for the protection of integrated circuits during ESD strikes. The anode (pwell contact) is connected to Vss or ground and the cathode (N+ diffusion) is connected to an input/output (I/O) pin. During an ESD strike on the I/O pin the N+/pwell diode becomes forward biased shorting the ESD current to ground. Because the path length of the ESD current is long, the turn on time of this ESD diode is sometimes slower than the rise time of the ESD current pulse. This results in voltage overshoot before the STI ESD protection diode turns on. This voltage overshoot may damage the integrated circuit.
A gate spaced PN ESD protection diode in which a transistor gate which is shorted to the anode (pwell contact) electrically isolates an N+ to pwell diode from the pwell contact may be used to avoid voltage overshoot. The current path of the gate spaced ESD protection diode is significantly shorter than the STI spaced diodes so the turn on time is significantly faster. An issue with the gate spaced ESD protection diode is higher capacitance than the STI spaced diode which degrades integrated circuit performance at high frequency.
A gate spaced NP ESD protection diode in which a transistor gate which is shorted to the cathode (nwell contact) electrically isolates a P+ to nwell diode from the nwell contact may be used to short ESD current on I/O pins to Vdd to protect the integrated circuit from damage.
After an ESD strike time is required for the ESD diode to reform the reverse biased depletion region. This recovery time limits high frequency performance of the gate spaced ESD protection diode and the high frequency performance of the integrated circuit.
It is desired to have ESD circuit protection with fast turn-on to avoid voltage overshoot and low capacitance along with fast recovery time to avoid circuit performance degradation at high frequencies.